Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, processors, and so forth).
The interconnect structure, CLBs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One such FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3–75 through 3–96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000”, published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and any other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Because of the large number of possible configurations in a PLD, testing a large PLD can be a time-consuming task. Ideally, every programmable element in the device is tested. A typical method of testing an FPGA, for example, is to create a design and an associated test pattern that together test one or more specific programmable resources of the PLD. Another design and test pattern are created to test other resources, and so forth. The designs are then sequentially loaded into the FPGA and tested using the associated test patterns. Because an FPGA can include millions of programmable elements, a large number of test patterns can be required to perform a thorough test.
A PLD bitstream can include millions of bits. Therefore, the process of loading a configuration bitstream into a PLD can take a significant amount of time, particularly for the larger devices. Hence, repeating the configuration process a large number of times during the testing process can take an undesirably long time, long enough to significantly impact the cost of the PLD to consumers.
Therefore, it is desirable to find methods of testing the programmable elements of PLDs using a minimal amount of configuration time during the test sequence.
PLD interconnect structures typically include interconnect lines of various lengths and types. These interconnect lines are programmably interconnected to the logic blocks and to other interconnect lines using programmable interconnect points (PIPs). For example, two interconnect lines can be coupled together by enabling a CMOS pass gate (a simple PIP) that programmably interconnects the two lines. U.S. Pat. No. 5,914,616 describes in detail the interconnect structure of the Xilinx Virtex FPGAs, and is hereby incorporated herein by reference.
One useful type of interconnect line is an interconnect line driven by a large number of programmable buffers. In some FPGAs, these buffers can be tristated using a signal supplied by user logic. In others, the buffers can only be tristated by appropriately setting or resetting one or more configuration memory cells. In some architectures, the buffers can be tristated using either method. Some FPGAs include more than one type of programmable buffer. In all cases, using currently known methods, testing these buffers requires successively reconfiguring the PLD between each test pattern to enable each buffer in turn. As previously described, this process can add significantly to the time required to test the PLD.
Therefore, it is desirable to provide improved methods of testing interconnect lines in PLDs that minimize testing time. Further, it is desirable to provide improved methods of testing interconnect lines driven by large numbers of programmable buffers.